1. Field of the Invention
This invention relates to the field of semiconductor integrated circuit fabrication and, in particular, to the fabrication of capacitors in small dynamic random access memory cells.
2. Background Art
The memory cells of dynamic random access memories (DRAMS) include two major components: a field effect transistor and a capacitor. It is well known in the art of semiconductor fabrication to use planar capacitors within DRAM cells. However, in DRAM cells that utilized conventional planar capacitors (such as the one depicted in prior art FIG. 1), more integrated circuit surface area was dedicated to the planar capacitor 11 than to the field effect transistor (FET) 12.
The gate 13 of the FET 12 and a word line 14 were formed from an etched polycrystalline silicon layer in these memory cells. A bit line 15 was connected to an access node junction 16. The planar capacitor 11 had a lower plate formed from the n+ silicon substrate extension 17 of the storage node junction 18 of the FET 12. An upper capacitor plate (or field plate) 19 was formed from a layer of conductively doped polycrystalline silicon. The substrate extension 17 was electrically insulated from the upper plate 19 by a dielectric layer 20. Planar capacitors such as the planar capacitor 11 generally proved to be adequate for use in DRAM integrated circuits up to approximately the one megabit level. However, planar capacitors constructed with conventional dielectric materials were not usable for the small memory cell sizes required beyond the one megabit DRAM level.
As memory cell size and therefore capacitor size shrank, several problems increased with respect to the fabrication of cell capacitors. For example, the problems that increased as capacitors shrank included rapid dissipation of the charge within the memory cell, resulting in "soft" errors, and reduction of the sense amp differential signal. This degraded noise sensitivity and made it more difficult to provide appropriate signal selectivity. Additionally, as cell capacitance decreased the cell refresh time generally shortened. Shorter refresh times required more frequent interruptions for refresh overhead.
Furthermore, as component density in integrated circuit memories increased, the shrinkage of memory cell size resulted in a number of other problems in addition to the problems associated with smaller capacitors. Among the other resulting problems was the problem of dopant out diffusion when forming the transistors of the memory cells. In order to form transistors, dopants must be implanted in regions of the semiconductor material. However, the dopants tended to diffuse out of the transistor regions when the transistors were heated during subsequent integrated circuit processing steps, for example, during the reoxidation anneal of the dielectric layer of the cell capacitor.
In prior art methods of DRAM cell fabrication, the problems caused by out diffusion of dopants from transistor regions were relatively small. However, as DRAM cell sizes continued to shrink, the channel lengths of transistors such as the FET 12 also had to shrink. Additionally, in smaller memory cell sizes, the junctions of transistors such as the FET 12 were required to be more shallow. When this occurred, the problem of out diffusion caused by subsequent heating steps increased. Dealing with out diffusion problems in the smaller cell geometries required tighter process control. Tighter process control added expense to the fabrication process.
Several methods for providing adequate cell capacitance in view of shrinking cell size have been developed. One well known method involved the creation of trench capacitors in the cell substrate. FIG. 2 depicts a DRAM cell that included a typical trench capacitor 21. Similar in concept to the planar capacitor 11 of FIG. 1, the trench capacitor 21 included a trench that was used to provide greater plate area, and hence, greater storage capacitance within the memory cell. The lower plate 22 of the trench capacitor 21 could be formed from the n+ doped silicon substrate or from a polycrystalline silicon layer which lined a trench cut in the n+ doped silicon substrate. The upper plate 23 of the trench capacitor 21 was formed from a layer conductively doped polycrystalline silicon. The lower plate 22 and the upper plate 23 were electrically insulated from each other with a dielectric layer 24.
The dielectric layer 24 of the trench capacitor 21 was typically deposited using a conventional chemical vapor deposition method. After deposition of the dielectric layer 24 a reoxidation anneal of the dielectric layer 24 was performed at atmospheric pressure. The typical temperature for the reoxidation anneal of the dielectric layer 24 was in excess of 800.degree. C. Annealing at temperatures this high contributed heavily to the thermal budget of the fabrication of the DRAM cell, thereby adding expense to the fabrication process. Additionally, during the reoxidation anneal of the dielectric layer 24 the diffusion regions of the FET 12 were heated to high temperatures as well as the dielectric layer 24. The heating of the diffusion regions of the FET 12 contributed to out diffusion of dopants from the diffusion regions of the FET 12 as previously described.
Another way to provide adequate cell capacitance in view of shrinking cell size was providing a dielectric material having a higher dielectric constant. Using a capacitor dielectric material having a higher dielectric constant to form dielectric layer 24 provided a larger capacitance in the same surface area of the FET 12. For this reason capacitors within DRAM cells often used a silicon nitride film as a dielectric layer rather than a silicon dioxide film. The dielectric constant of silicon nitride film is 1.5 to 2 times larger than that of the thermally grown silicon dioxide film used in the storage capacitors of conventional cells. The greatly increased dielectric constant of silicon nitride permitted increased capacitance in a predetermined cell surface area. Moreover, the frequency dispersion of the silicon nitride film dielectric constant was very small. Accordingly, the use of silicon nitride film in the storage capacitors of the smaller memory cells was preferred over the use of silicon dioxide.
However, dielectric materials within capacitors must also have as small a leakage current as possible in order to form a lossless capacitor. Silicon nitride has less desirable leakage current properties than silicon dioxide. In particular, the leakage current through silicon nitride films is larger than through silicon dioxide films that are thermally grown on silicon substrate because the energy bandgap of silicon dioxide is more narrow. The energy bandgap of silicon is 5 eV and the energy bandgap of silicon dioxide is 8 eV.
It is known in the prior art of forming capacitors within semiconductor integrated circuits that reoxidizing a layer of silicon nitride enough to form a thin oxide layer upon the surface of the silicon nitride reduced the leakage current of a silicon nitride film. Furthermore, it was determined that use of the oxide layer provided generally acceptable storage properties, including satisfactory breakdown voltage, where the breakdown voltage of the films was defined as the voltage at which a leakage current of 0.1 A/cm.sup.2 or destructive breakdown of the films occurred.
For example, in a typical prior art method, a forty nanometer thick silicon nitride layer was deposited by chemical vapor deposition using SiH.sub.4 and NH.sub.3 gases to form a dielectric layer of a capacitor of a DRAM cell such as the dielectric layer 24 of the FET 12. Very thin oxides were formed on the silicon nitride film surfaces by the reoxidation anneal process. Practice confirmed that the oxides formed in this manner were effective to sufficiently reduce the leakage current. Very good results were obtained with silicon nitride films, preferably in the range of forty to eighty angstroms thick, with thin oxides of approximately three nanometer thickness on their surfaces from oxidation treatment.
Therefore, in general, in order to obtain the advantages of the high dielectric constant of the silicon nitride a reoxidation anneal of the silicon nitride was required. This contributed to the thermal budget of the fabrication process and to out diffusion of dopants from the transistor regions.
Though the dielectric constant of the silicon nitride film was reduced somewhat by the oxidation treatment, it remained sufficiently large to provide the required capacitance. The leakage current through the silicon nitride film is bulk limited and it did not change with electrode material, electrode flatness or applied voltage polarity. This is very different from the leakage current through fully grown silicon dioxide films which is electrode limited.
Another structure for providing the storage capacitance required in DRAM cells as the size of the memory cells shrank, in addition to the trench structures and higher dielectric constant material in the capacitors, was a stacked capacitor structure on the DRAM cell surface. FIG. 3 is a graphical representation of a typical DRAM cell that included a stacked capacitor 31. The lower plate 32 of the stacked capacitor 31 was formed from a conductively doped n-type polycrystalline silicon layer that was in electrical contact with the silicon substrate 33 in the region of the FET storage node junction. The upper plate 34 of the stacked capacitor 31 was also formed from a conductively doped polycrystalline silicon layer.
The two polycrystalline silicon layers 32, 34, serving as the capacitor electrodes of the stacked capacitor 31, were separated by a dielectric layer 35. The dielectric layer 35 of the stacked capacitor 31 could be annealed in substantially the same manner as that previously described with respect to the reoxidation anneal of dielectric layer 24 of the trench capacitor 21 to form a thin layer of oxide on the surface of the dielectric layer 34. The lower plate 32 and the upper plate 34 of the stacked capacitor 31 were both stacked on top of the FET 12 and on top of an adjacent word line 36. The stacking approach to building capacitors in DRAM cells provided additional capacitance in a small memory cell and therefore provided an alternate solution to the trench capacitor method. However, it did not solve the problem of out diffusion from the diffusion regions of the transistors of the memory cells during the reoxidation anneal of the dielectric layers of the stacked capacitors and other high temperature steps of the fabrication process.
It is therefore an object of the present invention to provide an improved method for fabricating capacitors within very small DRAM cells wherein the capacitors have suitable storage properties including suitable capacitance, breakdown voltage and sense amp differential signal.
It is a further object of the present invention to provide a reduced thermal budget for the fabrication of DRAM cells having capacitors with reoxidized dielectric layers.
It is a further object of the present invention to sufficiently reduce the out diffusion of dopants from transistor regions within the transistors of DRAM cells to permit formation of shallow transistor junctions and short transistor channels without a requirement for tight control of the fabrication process in small DRAM cells.
These and other objects and advantages of the present invention will become more fully apparent from the description and from the claims which follow or may be learned by the practice of the invention.